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ds05-11433-1e fujitsu semiconductor data sheet memory mobile fcram tm cmos 128 m bit (8 m word 16 bit) mobile phone application specific memory mb82dbr08163a - 70l description the fujitsu mb82dbr08163a is a cmos fast cycle ra ndom access memory (fcram*) with asynchronous static random access memory (sram) interface contai ning 134,217,728 storages access ible in a 16-bit format. mb82dbr08163a is utilized using a fujitsu advanced fcram core technology and improved integration in comparison to regular sram. the mb82dbr08163a adopts asynchron ous page mode and synchronous burs t mode for fast memory access as user configurable options. this mb82dbr08163a is suited fo r mobile applications such as cellular handset and pda. * : fcram is a trademark of fujitsu limited, japan product lineup features ? asynchronous sram interface fast access time : t ce = 70 ns max 8 words page access capability : t pa a = 20 ns max burst read/write access capability : t ac = 11 ns max low voltage operating condition : v dd = 2.6 v to 3.1 v v ddq = 1.65 v to 1.95 v wide operating temperature : t a = -30 c to +85 c byte control by lb and ub low-power consumption : i dda1 = 35 ma max i dds1 = 300 a max various power down mode : sleep 16 m-bit partial 32 m-bit partial shipping form : wafer/chip parameter mb82dbr08163a-70l access time (max) (t ce , t aa ) 70 ns clk access time (max) (t ac ) 11 ns active current (max) (i dda1 ) 35 ma standby current (max) (i dds1 ) 300 a power down current (max) (i ddps ) 10 a
mb82dbr08163a- 70l 2 pin description note : refer to " package for engineering samples" for additi onal pin descriptions of fbga package supply. pin name description a 22 to a 0 address input ce 1 chip enable 1 (low active) ce2 chip enable 2(high active) we write enable (low active) oe output enable (low active) lb lower byte control (low active) ub upper byte control (low active) clk clock input adv address valid input (low active) wait wait output dq 8 to dq 1 lower byte data input/output dq 16 to dq 9 upper byte data input/output v dd power supply voltage v ddq i/o power supply voltage v ss ground
mb82dbr08163a- 70l 3 block diagram v dd v ddq v ss a 22 to a 3 a 2 to a 0 ce2 ce1 adv we oe lb ub wait clk d q 16 to dq 9 dq 8 to dq 1 mode controller command decoder address latch & buffer burst address counter address controller memory core controller bus controller read amp write amp parallel to serial conversion serial to parallel conversion memory cell array 134,217,728 bits i/o buffer burst controller converter y controller x controller
mb82dbr08163a- 70l 4 function truth table 1. asynchronous operation (page mode) note : l = v il , h = v ih , x can be either v il or v ih , high-z = high impedance *1 : should not be kept this logic condition longer than 1 s. *2 : power down mode can be entered from st andby state and all output are in high-z state. data retention depends on the selection of partial size for power down program. refer to "power down" in " functional description" for the details. *3 : "l" for address pass through and "h" fo r address latch on the rising edge of adv . *4 : oe can be v il during write operation if the fo llowing conditions are satisfied; (1) write pulse is initiated by ce 1. see "(14) asynchronous read/write timing 1-1 (ce 1 control)" in " timing diagrams". (2) oe stays v il during write cycle. *5 : can be either v il or v ih but must be valid before read or write. *6 : output of upper and lower byte data is ei ther valid or high-z depending on the level of lb and ub input. mode ce2 ce 1clkadv we oe lb ub a 22 to a 0 dq 8 to dq 1 dq 16 to dq 9 wait standby (deselect) h h x x x x x x x high-z high-z high-z output disable* 1 hl x *3 h h x x *5 high-z high-z high-z output disable (no read) x*3 hl h h valid high-z high-z high-z read (upper byte) x *3 h l valid high-z output valid high-z read (lower byte) x *3 l h valid output valid high-z high-z read (word) x *3 l l valid output valid output valid high-z page read x *3 l/h l/h valid *6 *6 high-z no write x *3 lh* 4 h h valid invalid invalid high-z write (upper byte) x *3 h l valid invalid input valid high-z write (lower byte) x *3 l h valid input valid invalid high-z write (word) x *3 l l valid input valid input valid high-z power down* 2 l x x x x x x x x high-z high-z high-z
mb82dbr08163a- 70l 5 2. synchronous operation (burst mode) note : l = v il , h = v ih , x can be either v il or v ih , = valid edge, = rising edge of low pulse, high-z = high impedance *1 : should not be kept this logic condition longer than 4 s. *2 : power down mode can be entered from st andby state and all output are in high-z state. data retention depends on the selection of partial size for power down program. refer to "power down" in ? functional description? for the details. *3 : valid clock edge shall be set on either rising or fa lling edge through cr set. clk must be started and stable prior to memory access. *4 : can be either v il or v ih except for the case the both of oe and we are v il . it is prohibited to bring the both of oe and we to v il . *5 : when device is operating in "we single clock pulse control" mode, we is don't care once write operation is determined by we low pulse at the beginning of write access together with address latching. burst write suspend feature is not supported in "we single clock pulse control" mode. *6 : can be either v il or v ih but must be valid before read or write is determined. and once lb and ub input levels are determined, they must not be changed until the end of burst. *7 : once valid address is determined, in put address must not be changed during adv = l. *8 : if oe = l, output is either invalid or high-z depending on the level of lb and ub input. if we = l, input is invalid. if oe = we = h, output is high-z. *9 : outputs is either valid or high-z depending on the level of lb and ub input. *10 : input is either valid or invalid depending on the level of lb and ub input. *11 : output is either high-z or invalid depending on the level of oe and we input. *12 : keep the level from previous cycle exc ept for suspending on last data. refer to "wait output function" in " functional description" for the details. *13 : wait output is driven in high level during burst write operation. mode ce2 ce 1clkadv we oe lb ub a 22 to a 0 dq 8 to dq 1 dq 16 to dq 9 wait standby(deselect) h h x x x x x x x high-z high-z high-z start address latch* 1 l * 3 x* 4 x* 4 x* 6 x* 6 valid* 7 high-z* 8 high-z* 8 high-z* 11 advance burst read to next address* 1 * 3 h h l x output valid* 9 output valid* 9 output valid burst read suspend* 1 * 3 h high-z high-z high* 12 advance burst write to next address* 1 * 3 l* 5 h input valid* 10 input valid* 10 high* 13 burst write suspend* 1 * 3 h* 5 input invalid input invalid high* 12 terminate burst read x h x high-z high-z high-z terminate burst write x x h high-z high-z high-z power down* 2 l x x x x x x x x high-z high-z high-z
mb82dbr08163a- 70l 6 state diagram note : assuming all the parameters specified in ac characteristics are satisfied. refer to the " functional description", "2. ac characteristics" in " electrical characteristics", and " timing dia- grams" for details. ce2 = h ce2 = l @m = 1 @m = 0 ce2 = h ce2 = l power down power up pause time standby cr set standby power down asynchronous operation (page mode) common state ? initial/standby state synchronous operation (burst mode) ce2 = ce1 = h ce1 = l ce1 = h ce1 = l & oe = l ce1 = h ce1 = h ce1 = l & we = l we = h we = l oe = h oe = l asynchronous operation standby write read output disable byte control @oe = l byte control address change or byte control ce2 = ce1 = h ce1 = h ce1 = h ce1 = h we = h we = l oe = h oe = l ce1 = h ce1 = l, adv low pulse, & we = l ce1 = l, adv low pulse, & oe = l synchronous operation standby write suspend read suspend write read adv low pulse (@bl = 8 or 16, and after burst operation is completed) adv low pulse adv low pulse
mb82dbr08163a- 70l 7 functional description this device supports asynchronous read, page read & normal write operation and synchronous burst read and burst write operation for faster memory access and feat ures three kinds of power down modes for power saving as user configurable option. ? power-up it is required to follow the power-up timing to start execut ing proper device operation. refer to "power-up timing". after power-up, the device defaults to asynchronous page read & normal wr ite operation mode with sleep power down feature. ? configuration register the configuration register(cr) is us ed to configure the type of device function among optional features. each selection of features is set through cr set sequence afte r power-up. if cr set sequence is not performed after power-up, the device is configured for asynchronous operation with sleep power down feature as default con- figuration. ? cr set sequence the cr set requires total 6 read/write cycles with unique address. operation other than read/write operation requires that device being in standby mode . following table shows the detail sequence. the first cycle is to read from most significant address(msb). the second and third cycles are to write to msb. if the se cond or third cycle is written into the different address, the cr set is cancelled and the data written by the sec ond or third cycle is valid as a normal write operation. it is recommended to write back the data(rda) read by first cycle to msb in order to secure the data. the forth and fifth cycles are to write to msb. the data of forth and fifth cycles is don't-care. if the forth or fifth cycle is written into different address, the cr set is al so cancelled, but write data may not be written as normal write operation. the last cycle is to read from specific address ke y for mode selection. and read data(rdb) is invalid. once this cr set sequence is performed from an initial cr set to the other new cr set, the written data stored in memory cell array may be lost. so, it should perform the cr set sequence prior to regular read/write operation if necessary to change fr om default configuration. cycle # operation address data #1 read 7fffffh (msb) read data (rda) #2 write 7fffffh rda #3 write 7fffffh rda #4 write 7fffffh x #5 write 7fffffh x #6 read address key read data (rdb)
mb82dbr08163a- 70l 8 ? address key the address key has the following format. *1: a 22 , a 21 , a 8 and a 6 to a 0 must be all "1" in any cases. *2: it is prohibited to apply this key. *3: if m = 0, all the registers must be set wi th appropriate key input at the same time. *4: if m = 1, ps must be set with appropriate key input at the same time. except for ps, all the other key inputs must be "1". *5: burst read & single wr ite is not supported at we single clock pulse control. address pin register name function key description note a 22 , a 21 ?? 1 unused bits must be 1 *1 a 20 , a 19 ps partial size 00 32 m-bit partial 01 16 m-bit partial 10 reserved for future use *2 11 sleep [default] a 18 to a 16 bl burst length 000 reserved for future use *2 001 reserved for future use *2 010 8 words 011 16 words 100 reserved for future use *2 101 reserved for future use *2 110 reserved for future use *2 111 continuous a 15 mmode 0 synchronous mode (burst read / write) *3 1 asynchronous mode [default] (page read / normal write) *4 a 14 to a 12 rl read latency 000 reserved for future use *2 001 3 clocks 010 4 clocks 011 5 clocks 1xx reserved for future use *2 a 11 bs burst sequence 0 reserved for future use *2 1 sequential a 10 sw single write 0 burst read & burst write 1 burst read & single write *5 a 9 ve valid clock edge 0 falling clock edge 1 rising clock edge a 8 ?? 1 unused bits must be 1 *1 a 7 wc write control 0 we single clock pulse control without write suspend function *5 1we level control with write suspend function a 6 to a 0 ?? 1 unused bits must be 1 *1
mb82dbr08163a- 70l 9 ? power down the power down is low power idle state controlled by ce2. ce2 low drives the device in power down mode and maintains low power idle state as long as ce2 is kept low. ce2 high resumes the device from power down mode. this device has three power down modes, sl eep, 16 m-bit partial, and 32 m-bit partial. the selection of power down mode is set through cr set sequence. each mode has following data retention features. the default state after power-up is sleep and it is the lowest power consumption but all data will be lost once ce2 is brought to low for power down. it is not required to perform cr set sequence to set to sleep mode after power-up in case of asynchronous operation. ? burst read/write operation synchronous burst read/write operation provides faster me mory access that synchronized to microcontroller or system bus frequency. configuration re gister(cr) set is required to perform burst read & write operation after power-up. once cr set sequence is pe rformed to select synchronous burst mode, the device is configured to synchronous burst read/write operation mode with correspon ding rl and bl that is set through cr set sequence together with operation mode. in order to perform synchr onous burst read & write oper ation, it is required to control new signals, clk, adv and wait that low power srams don?t have. mode data retention size retention address sleep [default] no n/a 16 m-bit partial 16 m bits 000000h to 0fffffh 32 m-bit partial 32 m bits 000000h to 1fffffh
mb82dbr08163a- 70l 10 ? clk input function the clk is input signal to synchronize memory to mi crocontroller or system bus frequency during synchronous burst read & write operation. the clk input increments device internal address counter and the valid edge of clk is referred for latency counts from address latch, bu rst write data latch, and burst read data output. during synchronous operation mode, clk input must be supplied except for standby state and power down state. clk is don't care during asynchronous operation. rl bl high high-z high-z clk adv ce1 oe we w ait dq q 1 q 2 q bl burst read operation valid address address rl-1 bl high high-z high-z clk adv ce1 oe we w ait dq d 1 d 2 d bl burst write operation valid address address
mb82dbr08163a- 70l 11 ? adv input function the adv is input signal to latch valid address. it is applic able to synchronous operation as well as asynchronous operation. adv input is active during ce 1 = l and ce 1 = h disables adv input. all addresses are determined on the rising edge of adv . during synchronous burst read/write operation, adv = h disables all address inputs. once adv is brought to high after valid address latch, it is inhibited to bring adv low until the end of burst or until burst operation is terminated. adv low pulse is mandatory for synchronous burst read/write operation mode to latch the valid address input. during asynchronous operation, adv = h also disables all address inputs. adv can be tied to low during asynchronous operation and it is not necessary to control adv to high. ? wait output function the wait is output signal to indicate data bus status when the device is operating in synchronous burst mode. during burst read operation, wait output is enabled after s pecified time duration from oe = l or ce 1 = l whichever occurs last. wait output low indicates data output at next clock cycle is invalid, and wait output becomes high one clock cycle prior to valid data output. during oe read suspend, wait output doesn?t indicate data bus status but carries the same level from previ ous clock cycle (kept high) ex cept for burst read suspend on the final data output. if final read data output is suspended, wait output becomes high impedance after specified time duration from oe = h. during burst write operation, wait output is valid to high level after specified time duration from we = l or ce 1 = l whichever occurs last and kept high for entire write cycles including we write suspend. the actual write data latching starts on the appropriate clock edge with respec t to valid clock edge, read latency, and burst length. during we write suspend, wait output doesn?t indicate data bus status but carries the same level from previous clock cycle (kept high) except for write suspend on the final data input. if final write data input is suspended, wait output becomes high impedance afte r specified time duration from we = h. this device doesn?t incur additional output delay agains t crossing device-row boundary or internal refresh op- eration. therefore, the burst operation is always started after fixed latency with respec t to read latency. and there is no waiting cycle asserted in t he middle of burst operation except for burst read or write suspend by oe brought to high or we brought to high. thus, once wait output is enabled and brought to high, wait output keeps high level until the end of burst or unt il the burst operation is terminated. when the device is operating in asynchronous mode, wait output is always in high impedance.
mb82dbr08163a- 70l 12 ? latency read latency (rl) is the number of clock cycles betwee n the address being latched and first read data becoming available during synchronous burst read operation. it is set through cr set sequence after power-up. once specific rl is set through cr set sequ ence, write latency, that is the number of clock cycles between address being latched and first write data being latched, is automatically set to rl-1. the burst operation is always started after fixed latency with respect to read latency set in cr. rl = 3 0 rl = 4 rl = 5 12 3 4 5 6 clk adv ce1 wait dq wait dq wait dq wait dq wait dq wait dq q 1 q 2 q 3 q 4 q 5 d 1 d 3 d 4 d 5 d 6 q 3 q 4 d 1 d 4 d 5 q 2 q 3 d 2 d 1 d 3 d 4 q 1 d 3 d 2 q 1 q 2 d 2 high-z high-z high-z high-z high-z high-z valid address [output] [input] oe or we address [output] [input] [output] [input]
mb82dbr08163a- 70l 13 ? address latch by adv the adv latches valid address presence on address inputs. during synchronous burst read/write operation mode, all the address are deter mined on the rising edge of adv when ce 1 = l. the specified minimum value of adv = l setup time and hold time against valid edge of clock where rl count is begun must be satisfied. valid address must be determined with specified setup time against either the falling edge of adv or falling edge of ce 1 whichever comes late. and the determined valid address must not be changed during adv = l period. ? burst length burst length is the number of word to be read or wri tten during synchronous burst r ead/write operation as the result of a single address latch cycle. it can be se t on 8,16 words boundary or continuous for entire address through cr set sequence. the burst type is sequential that is incremental decoding scheme within a boundary address. starting from initial address being latched, device internal address counter assigns +1 to the previous address until reaching the end of boundary address and then wrap round to least significant address (= 0). after completing read data output or write data latch for the set burst length, operation automatically ended except for continuous burst length. when cont inuous burst length is set, read/write is endless unless it is terminated by the rising edge of ce 1. ? single write single write is synchronous write operat ion with burst length = 1. the device can be configured either to "burst read & single write" or to "burst read & burst write" through cr set sequence. once the device is configured to "burst read & single write" mode, the burst length fo r synchronous write operation is always fixed 1 regardless of bl values set in cr, while burst length for read is in accordance with bl values set in cr.
mb82dbr08163a- 70l 14 ? write control the device has two types of we signal control method, "we level control" and "we single clock pulse control", for synchronous burst write operation. it is configured through cr set sequence. 0 12 3 4 5 6 rl = 5 t wld t ckwh t clth t wlth high-z high-z clk adv ce1 wait dq wait dq we we d 1 d 2 d 3 d 4 d 1 d 2 t wsck t wlth d 4 d 3 valid address address we level control we single clock pulse control [input] [input]
mb82dbr08163a- 70l 15 ? burst read suspend burst read operation can be suspended by oe high pulse. during burst read operation, oe brought to high from low suspends burst read operation. once oe is brought to high with the s pecified setup time against clock where the data being suspended, the device internal c ounter is suspended, and t he data output becomes high impedance after specified time duration. it is inhibited to susp end the first data output at the beginning of burst read. oe brought to low from high resumes burst read operation. once oe is brought to low, data output becomes valid after specified time duration, and internal address counter is reactivated. the last data output being sus- pended as the result of oe = h and first data outpu t as the result of oe = l are from the same address. in order to guarantee to output last data before suspensi on and first data after resump tion, the specified minimum value of oe hold time and oe setup time against clock edge must be satisfied respectively. ? burst write suspend burst write operation can be suspended by we high pulse. during burst write operation, we brought to high from low suspends burst write operation. once we is brought to high with the specified setup time against clock where the data being suspended, devi ce internal counter is suspended, data input is ignored. it is inhibited to suspend the first data input at the beginning of burst write. we brought to low from high resumes burst write operation. once we is brought to low, data input becomes valid after specified time duration, and internal address counter is reactivated. the write address of the cycle where data being suspended and the first write address as the result of we = l are the same address. in order to guarantee to latch the last data input befo re suspension and first data input after resumption, the specified minimum value of we hold time and we setup time against clock edge must be satisfied respectively. burst write suspend function is availabl e when the device is operating in we level controlled burst write only. clk oe w ait dq t ckoh t osck t osck t ckoh t ac t ac t ac t olz t ckqx t ckqx t ckqx t cktv t ac t ohz q 1 q 2 q 3 q 4 q 2 clk we w ait dq t ckwh t wsck t wsck t ckwh t dhck t dsck d 1 d 3 d 4 d 2 d 2 t dsck t dsck t dsck t dhck t dhck high
mb82dbr08163a- 70l 16 ? burst read termination burst read operation can be terminated by ce 1 brought to high. if bl is set on continuous, burst read operation is continued endless unless terminated by ce 1 = h. it is inhibited to terminate burst read before first data output is completed. in order to guarantee last data output, the specified minimum value of ce 1 = l hold time from clock edge must be satisfied. after terminat ion, the specified minimum recovery time (t trb ) is required to start new access. ? burst write termination burst write operation can be terminated by ce 1 brought to high. if bl is set on continuous, burst write operation is continued endless unless terminated by ce 1 = h. it is inhibited to terminat e burst write before first data input is completed. in order to guarant ee last data input being latched, th e specified minimum values of ce 1 = l hold time from clock edge must be satisfied. after term ination, the specified minimum recovery time (t trb ) is required to start new access. t trb clk adv ce1 w ait dq oe t ckclh t chz t ckoh t ohz t chtz t ac t ckqx high-z q 2 q 1 address valid address t trb clk adv ce1 w ait dq we t ckclh t chck t ckwh t chtz t dsck high-z d 2 d 1 t dsck t dhck t dhck address valid address
mb82dbr08163a- 70l 17 absolute maximum ratings * : all voltages are referenced to v ss = 0 v. warning: semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. recommended operating conditions *1 : all voltages are referenced to v ss = 0 v. *2 : maximum dc voltage on input and i/o pins is v ddq + 1.0 v. during voltage transitions, inputs may overshoot to v ddq + 1.0 v for periods of up to 5.0 ns. *3 : minimum dc voltage on input or i/o pins is -0.3 v. during voltage transitions, inputs may undershoot v ss to -1.0 v for periods of up to 5.0 ns. warning: the recommended operating conditions are require d in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max voltage of v dd supply relative to v ss *v dd ? 0.5 + 3.6 v voltage of v ddq supply relative to v ss *v ddq ? 0.5 + 2.6 v voltage at any pin relative to v ss *v in , v out ? 0.5 + 2.6 v short circuit output current i out ? 50 + 50 ma storage temperature tstg ? 55 + 125 c parameter symbol value unit min max power supply voltage* 1 v dd 2.6 3.1 v i/o power supply voltage* 1 v ddq 1.65 1.95 v ground v ss 00v high level input voltage* 1, * 2 v ih v ddq 0.8 v ddq + 0.2 v low level input voltage* 1, * 3 v il ? 0.3 v ddq 0.2 v ambient temperature t a ? 30 + 85 c
mb82dbr08163a- 70l 18 electrical characteristics 1. dc characteristics (at recommended operating condi tions unless otherwise noted) notes : ? all voltages are referenced to v ss = 0 v. ? dc characteristics are measured after following power-up timing. ? i out depends on the output load conditions. parameter symbol test conditions value unit min max input leakage current i li v ss v in v ddq ? 1.0 + 1.0 a output leakage current i lo 0 v v out v ddq , output high impedance ? 1.0 + 1.0 a output high voltage level v oh v ddq = v ddq (min), i oh = ? 0.5 ma 1.4 ? v output low voltage level v ol i ol = 1 ma ? 0.4 v v dd power down current i ddps v dd = v dd (max), v ddq = v ddq (max), v in = v ih or v il , ce2 0.2 v sleep ? 10 a i ddp16 16 m-bit partial ? 120 a i ddp32 32 m-bit partial ? 150 a v dd standby current i dds v dd = v dd (max), v ddq = v ddq (max), v in (including clk) = v ih or v il , ce 1 = ce2 = v ih ? 1.5 ma i dds1 v dd = v dd (max), v ddq = v ddq (max), v in (including clk) 0.2 v or v in (including clk) v ddq ? 0.2 v, ce 1 = ce2 v ddq ? 0.2 v ? 300 a i dds2 v dd = v dd (max), v ddq = v ddq (max), t ck = min v in 0.2 v or v in v ddq ? 0.2 v, ce 1 = ce2 v ddq ? 0.2 v ? 350 a v dd active current i dda1 v dd = v dd (max), v ddq = v ddq (max), v in = v ih or v il , ce 1 = v il and ce2 = v ih , i out = 0 ma t rc /t wc = min ? 35 ma i dda2 t rc /t wc = 1 s ? 5ma v dd page read current i dda3 v dd = v dd (max), v ddq = v ddq (max), v in = v ih or v il , ce 1 = v il and ce2 = v ih , i out = 0 ma, t prc = min ? 15 ma v dd burst access current i dda4 v dd = v dd (max), v ddq = v ddq (max), v in = v ih or v il , ce 1 = v il and ce2 = v ih , t ck = t ck (min), bl = continuous, i out = 0 ma ? 30 ma
mb82dbr08163a- 70l 19 2. ac characteristics (1) asynchronous read operation (page mode) (at recommended operating condi tions unless otherwise noted) *1 : maximum value is applicable if ce 1 is kept at low without ch ange of address input of a 22 to a 3 . *2 : address should not be changed within minimum t rc . *3 : the output load 50 pf with 50 ? termination to v ddq 0.5 v. *4 : the output load 5 pf without any other load. *5 : applicable to a 22 to a 3 when ce 1 is kept at low. *6 : applicable only to a 2 , a 1 and a 0 when ce 1 is kept at low for the page address access. (continued) parameter symbol value unit notes min max read cycle time t rc 70 1000 ns *1, *2 ce 1 access time t ce ? 70 ns *3 oe access time t oe ? 40 ns *3 address access time t aa ? 70 ns *3, *5 adv access time t av ? 70 ns *3 lb , ub access time t ba ? 30 ns *3 page address access time t paa ? 20 ns *3, *6 page read cycle time t prc 20 1000 ns *1, *6, *7 output data hold time t oh 5 ? ns *3 ce 1 low to output low-z t clz 5 ? ns *4 oe low to output low-z t olz 5 ? ns *4 lb , ub low to output low-z t blz 0 ? ns *4 ce 1 high to output high-z t chz ? 20 ns *3 oe high to output high-z t ohz ? 20 ns *3 lb , ub high to output high-z t bhz ? 20 ns *3 address setup time to ce 1 low t asc ? 5 ? ns address setup time to oe low t aso 10 ? ns adv low pulse width t vpl 10 ? ns *8 adv high pulse width t vph 15 ? ns *8 address setup time to adv high t asv 5 ? ns address hold time from adv high t ahv 5 ? ns address invalid time t ax ? 10 ns *5, *9 address hold time from ce 1 high t chah ? 5 ? ns *10 address hold time from oe high t ohah ? 5 ? ns we high to oe low time for read t whol 25 1000 ns *11 ce 1 high pulse width t cp 15 ? ns
mb82dbr08163a- 70l 20 (continued) *7 : in case page read cycle is continued with keeping ce 1 stays low, ce 1 must be brought to high within 4 s. in other words, page read cycle must be closed within 4 s. *8 : t vpl is specified from the falling edge of either ce 1 or adv whichever comes late. the sum of t vpl and t vph must be equal or greater than t rc for each access. *9 : applicable to address access when at least two of address inputs are switched from previous state. *10 : t rc (min) and t prc (min) must be satisfied. *11 : if actual value of t whol is shorter than specified minimum values, the actual t aa of following read may become longer by the amount of subtracting actu al value from specified minimum value.
mb82dbr08163a- 70l 21 (2) asynchronous write operation (at recommended operating condi tions unless otherwise noted) *1 : maximum value is applicable if ce 1 is kept at low without any address change. *2 : minimum value must be equal or greater than the sum of write pulse width (t cw , t wp or t bw ) and write recovery time (t wr ). *3 : write pulse width is defined from high to low transition of ce 1, we , lb , or ub , whichever occurs last. *4 : t vpl is specified from the falling edge of either ce 1 or adv whichever comes late. the sum of t vpl and t vph must be equal or greater than t wc for each access. *5 : write recovery time is defined from low to high transition of ce 1, we , lb , or ub , whichever occurs first. *6 : if oe is low after minimum t ohcl , read cycle is initiated. in other word, oe must be brought to high within 5 ns after ce 1 is brought to low. *7 : if oe is low after new address input, read cycle is initiated. in other word, oe must be brought to high at the same time or before new address is valid. parameter symbol value unit notes min max write cycle time t wc 70 1000 ns *1, *2 address setup time t as 0 ? ns *3 adv low pulse width t vpl 10 ? ns *4 adv high pulse width t vph 15 ? ns *4 address setup time to adv high t asv 5 ? ns address hold time from adv high t ahv 5 ? ns ce 1 write pulse width t cw 45 ? ns *3 we write pulse width t wp 45 ? ns *3 lb , ub write pulse width t bw 45 ? ns *3 write recovery time t wr 0 ? ns *5 ce 1 high pulse width t cp 15 ? ns we high pulse width t whp 15 1000 ns lb , ub high pulse width t bhp 15 1000 ns data setup time t ds 15 ? ns data hold time t dh 0 ? ns oe high to ce 1 low setup time for write t ohcl ? 5 ? ns *6 oe high to address setup time for write t oes 0 ? ns *7 lb and ub write pulse overlap t bwo 30 ? ns
mb82dbr08163a- 70l 22 (3) synchronous operation - clock input (burst mode) (at recommended operating condi tions unless otherwise noted) *1 : clock period is defined between valid clock edges. *2 : clock transition time is defined between v ih (min) and v il (max) (4) synchronous operation - address latch (burst mode) (at recommended operating condi tions unless otherwise noted) *1 : t ascl is applicable if ce 1 is brought to low after adv is brought to low. *2 : t asvl is applicable if adv is brought to low after ce 1 is brought to low. *3 : t vpl is specified from the falling edge of either ce 1 or adv whichever comes late. *4 : applicable to the 1st valid clock edge. parameter symbol value unit notes min max clock period rl = 5 t ck 13 ? ns *1 rl = 4 18 ? ns *1 rl = 3 30 ? ns *1 clock high pulse width t ckh 4 ? ns clock low pulse width t ckl 4 ? ns clock transition time t ckt ? 3ns*2 parameter symbol value unit notes min max address setup time to ce 1 low t ascl ? 5 ? ns *1 address setup time to adv low t asvl ? 5 ? ns *2 address hold time from adv high t ahv 5 ? ns adv low pulse width t vpl 10 ? ns *3 adv low setup time to clk t vsck 4 ? ns *4 ce 1 low setup time to clk t clck 4 ? ns *4 adv low hold time from clk t ckvh 1 ? ns *4 burst end adv high hold time from clk t vhvl 13 ? ns
mb82dbr08163a- 70l 23 (5) synchronous read operation (burst mode) (at recommended operating condi tions unless otherwise noted) *1 : the output load 50 pf with 50 ? termination to v ddq 0.5 v. *2 : wait drives high at the beginning depending on oe falling edge timing. *3 : t cktv is guaranteed after t oltl (max) from oe falling edge and t osck must be satisfied. *4 : the output load 5 pf without any other load. *5 : once they are determined, they must not be changed until the end of burst read. *6 : defined from the low to high transition of ce 1 to the high to low transition of either adv or ce 1 whichever occurs late. parameter symbol value unit notes min max burst read cycle time t rcb ? 8000 ns clk access time t ac ? 11 ns *1 output hold time from clk t ckqx 3 ? ns *1 ce 1 low to wait low t cltl 520ns*1 oe low to wait low t oltl 020ns*1, *2 adv low to wait low t vltl 020ns*1 clk to wait valid time t cktv ? 11 ns *1, *3 wait valid hold time from clk t cktx 3 ? ns *1 ce 1 low to output low-z t clz 5 ? ns *4 oe low to output low-z t olz 5 ? ns *4 lb , ub low to output low-z t blz 0 ? ns *4 ce 1 high to output high-z t chz ? 20 ns *1 oe high to output high-z t ohz ? 20 ns *1 lb , ub high to output high-z t bhz ? 20 ns *1 ce 1 high to wait high-z t chtz ? 20 ns *1 oe high to wait high-z t ohtz ? 20 ns *1 oe low setup time to 1st data-output t olq 30 ? ns lb , ub setup time to 1st data-output t blq 26 ? ns *5 oe setup time to clk t osck 4 ? ns oe hold time from clk t ckoh 2 ? ns burst end ce 1 low hold time from clk t ckclh 2 ? ns burst end lb , ub hold time from clk t ckbh 2 ? ns burst terminate recovery time bl = 8, 16 t trb 26 ? ns *6 bl = continuous 70 ? ns *6
mb82dbr08163a- 70l 24 (6) synchronous write operation (burst mode) (at recommended operating condi tions unless otherwise noted) *1 : defined from the valid input edge to the high to low transition of either adv , ce 1, or we , whichever occurs last. and once lb , ub are determined, lb , ub must not be changed until the end of burst write. *2 : the output load 50 pf with 50 ? termination to v ddq 0.5 v. *3 : defined from the valid clock edge where last data-input being latched at the end of burst write to the high to low transition of either adv or ce 1 whichever occurs late for the next access. *4 : defined from the low to high transition of ce 1 to the high to low transition of either adv or ce 1 whichever occurs late for the next access. parameter symbol value unit notes min max burst write cycle time t wcb ? 8000 ns data setup time to clk t dsck 5 ? ns data hold time from clk t dhck 3 ? ns we low setup time to 1st data input t wld 30 ? ns lb , ub setup time for write t bs -5 ? ns *1 we setup time to clk t wsck 4 ? ns we hold time from clk t ckwh 2 ? ns ce 1 low to wait high t clth 520ns*2 we low to wait high t wlth 020ns*2 ce 1 high to wait high-z t chtz ? 20 ns *2 we high to wait high-z t whtz ? 20 ns *2 burst end ce 1 low hold time from clk t ckclh 2 ? ns burst end ce 1 high setup time to next clk t chck 4 ? ns burst end lb , ub hold time from clk t ckbh 2 ? ns burst write recovery time t wrb 26 ? ns *3 burst terminate recovery time bl = 8, 16 t trb 26 ? ns *4 bl = continuous t trb 70 ? ns *4
mb82dbr08163a- 70l 25 (7) power down parameters (at recommended operating condi tions unless otherwise noted) *1: applicable also to power-up. *2: applicable when 16 m-bit or 32 m-bit partial mode is set. (8) other timing parameters (at recommended operating condi tions unless otherwise noted) *1 : some data might be written into any address location if t chwx (min) is not satisfied. *2 : except for clk input transition time. *3 : the input transition time (t t ) at ac testing is 5 ns for asynchr onous operation and 3 ns for synchronous operation respectively. if actual t t is longer than 5 ns or 3 ns specified as ac test condition, it may violate ac specification of some timing parame ters. see " (9) ac test conditions". parameter symbol value unit notes min max ce2 low setup time for power down entry t csp 20 ? ns *1 ce2 low hold time after power down entry t c2lp 70 ? ns *1 ce 1 high hold time following ce2 high after power down exit [sleep mode only] t chh 300 ? s*1 ce 1 high hold time following ce2 high after power down exit [not in sleep mode] t chhp 70 ? ns *2 ce 1 high setup time following ce2 high after power down exit t chs 0 ? ns *1 parameter symbol value unit notes min max ce 1 high to oe invalid time for standby entry t chox 10 ? ns ce 1 high to we invalid time for standby entry t chwx 10 ? ns *1 ce2 high hold time after power-up t c2hl 50 ? s ce 1 high hold time following ce2 high after power-up t chh 300 ? s input transition time (except for clk) t t 125ns*2, *3
mb82dbr08163a- 70l 26 (9) ac test conditions description symbol test setup value unit notes input high level v ih ? v ddq 0.8 v input low level v il ? v ddq 0.2 v input timing measurement level v ref ? v ddq 0.5 v input transition time async. t t between v il and v ih 5ns sync. 3 ns v dd v ss 0.1 f 50 pf v ddq v ss 0.1 f 50 v ddq 0.5 v output device under test ac measurement output load circuit
mb82dbr08163a- 70l 27 timing diagrams (1) asynchronous read timing 1-1 (basic timing) t rc t ce t asc t chah t cp t chz t ohz t oe t ba t blz t olz t bhz t oh t asc ce1 oe dq l b , ub adv low valid data output (output) address address valid note : this timing diagram assumes ce2 = h and we = h.
mb82dbr08163a- 70l 28 (2) asynchronous read timing 1-2 (basic timing) t rc t ce t asc t cp t chz t ohz t oe t ba t blz t olz t bhz t oh t asc ce1 oe dq l b , ub adv t asv t vph t vpl t ahv t av note : this timing diagram assumes ce2 = h and we = h. valid data output (output) address address valid
mb82dbr08163a- 70l 29 (3) asynchronous read timing 2 (oe control & address access) note : this timing diagram assumes ce2 = h, adv = l and we = h. ce1 oe dq t rc t rc t aso t oe t ohz t olz t oh t oh t ohah t aa t aa t ax lb, ub low valid data output (output) address valid address valid address valid data output
mb82dbr08163a- 70l 30 (4) asynchronous read timing 3 (lb , ub byte control access) t rc t ax t ax t aa low t ba t ba t ba t blz t oh t blz t oh t oh t blz t bhz t bhz t bhz ce1 , oe lb ub note : this timing diagram assumes ce2 = h, adv = l and we = h. address valid data output address valid valid data output valid data output dq 16 to dq 9 (output) dq 8 to dq 1 (output)
mb82dbr08163a- 70l 31 (5) asynchronous read timing 4 (page address access after ce 1 control access) t rc t rc t prc t prc t prc t paa t paa t paa t chah t oh t oh t oh t oh t clz t asc t chz t ce ce1 oe dq lb , ub adv note : this timing diagram assumes ce2 = h and we = h. address valid (output) valid data output (normal access) valid data output (page access) address valid address vali d address valid address valid address (a 22 to a 3 ) address (a 2 to a 0 )
mb82dbr08163a- 70l 32 (6) asynchronous read timing 5 (random and page address access) t rc t rc t rc t aa l ow t paa t prc t aso t oe t ba t olz t blz t oh t oh t oh t oh t aa t rc t paa t prc t ax t ax ce1 oe lb , ub dq notes : ? this timing diagram assumes ce2 = h, adv = l and we = h. ? either or both lb and ub must be low when both ce 1 and oe are low. address valid (output) valid data output (normal access) valid data output (page access) address valid address valid address valid address valid address valid address (a 22 to a 3 ) address (a 2 to a 0 )
mb82dbr08163a- 70l 33 (7) asynchronous write timing 1-1 (basic timing) ce1 we l b, ub oe dq t wc t wr t wr t wr t as t as t as t cw t wp t bw t as t as t ohcl t as t ds t dh adv low t cp t whp t bhp note : this timing diagram assumes ce2 = h and adv = l. (input) address address valid valid data input
mb82dbr08163a- 70l 34 (8) asynchronous write timing 1-2 (basic timing) ce1 we l b, ub oe dq t wc t wr t wr t wr t as t as t as t cw t wp t bw t as t as t ohcl t as t ds t dh adv t cp t whp t bhp t ahv t asv t vph t vpl note : this timing diagram assumes ce2 = h. (input) address address valid valid data input
mb82dbr08163a- 70l 35 (9) asynchronous write timing 2 (we control) ce1 we l b, ub oe dq t wc t wc t wr t as t wp t wr t wp t as t ohah t oes t ohz t ds t dh t ds t dh low t whp note : this timing diagram assumes ce2 = h and adv = l. (input) address address valid valid data input address valid valid data input
mb82dbr08163a- 70l 36 (10) asynchronous write timing 3-1 (we , lb , ub byte write control) ce1 we ub lb t wc t wc t as t wp t wr t wp t as t ds t dh t ds t dh low t wr t whp note : this timing diagram assumes ce2 = h, adv = l and oe = h. dq 16 to dq 9 (input) address address valid valid data input address valid dq 8 to dq 1 (input) valid data input
mb82dbr08163a- 70l 37 (11) asynchronous write timing 3-2 (we , lb , ub byte write control) ce1 we ub lb t wc t wc t wr t as t bw t wr t bw t ds t dh t ds t dh low t as t whp note : this timing diagram assumes ce2 = h, adv = l and oe = h. address address valid valid data input address valid valid data input dq 16 to dq 9 (input) dq 8 to dq 1 (input)
mb82dbr08163a- 70l 38 (12) asynchronous write timing 3-3 (we , lb , ub byte write control) c e1 we ub lb t wc t wc t wr t as t bw t wr t bw t as t ds t dh t ds t dh low t whp note : this timing diagram assumes ce2 = h, adv = l and oe = h. address address valid valid data input address valid valid data input dq 16 to dq 9 (input) dq 8 to dq 1 (input)
mb82dbr08163a- 70l 39 (13) asynchronous write timing 3-4 (we , lb , ub byte write control) ce1 we ub lb t wc t wc t wr t bw t bwo t bwo t as t wr t bw t as t wr t bw t as t wr t bw t as t ds t dh t ds t dh t ds t dh t ds t dh low t bhp t bhp note : this timing diagram assumes ce2 = h, adv = l and oe = h. address address valid valid data input address valid valid data input valid data input valid data input dq 8 to dq 1 (input) dq 16 to dq 9 (input)
mb82dbr08163a- 70l 40 (14) asynchronous read/write timing 1-1 (ce 1 control) ce1 we l b, ub oe dq t chah t as t cp t ohcl t chz t oh t wc t cw t wr t asc t cp t ds t dh t rc t ce t chah t clz t oh notes : ? this timing diagram assumes ce2 = h and adv = l. ? write address is valid from either ce 1 or we of last falling edge. address write address write data input read address read data output
mb82dbr08163a- 70l 41 (15) asynchronous read/write timing 1-2 (ce 1, we , oe control) ce1 we l b, ub oe dq t chah t as t cp t ohcl t chz t oh t wc t wp t wr t asc t cp t oe t ds t dh t rc t ce t chah t olz t oh notes : ? this timing diagram assumes ce2 = h and adv = l. ? oe can be fixed low during write operation if it is ce 1 controlled write at read-write-read sequence. write address write data input read address read data output read data output address
mb82dbr08163a- 70l 42 (16) asynchronous read/write timing 2 (oe , we control) ce1 we l b, ub oe dq t ohah t wr t as t oes t ohz t oh t wc t wp t oe t ohz t ds t dh t rc t aa t ohah t olz t aso t oh low t whol notes : ? this timing diagram assumes ce2 = h and adv = l. ? ce 1 can be tied to low for we and oe controlled operation. address write address write data input read address read data output read data output
mb82dbr08163a- 70l 43 (17) asynchronous read/write timing 3 (oe , we , lb , ub control) ce1 we l b, ub oe dq t ohah t as t wr t oes t bhz t oh t wc t bw t ba t bhz t ds t dh t rc t aa t ohah t blz t aso t oh low t whol notes : ? this timing diagram assumes ce2 = h and adv = l. ? ce 1 can be tied to low for we and oe controlled operation. address read address write data input write address read data output read data output
mb82dbr08163a- 70l 44 (18) clock input timing (19) address latch timing (synchronous mode) c lk t ck t ck t ckh t ckl t ckt t ckt notes : ? stable clock input must be required during ce 1 = l. ? t ck is defined between valid clock edges. ? t ckt is defined between v ih (min) and v il (max). low clk a dv ce1 t ascl t vsck t ckvh t vpl t clck t ahv t asvl t vsck t ckvh t ahv t vpl notes : ? case #1 is the timing when ce 1 is brought to low after adv is brought to low. case #2 is the timing when adv is brought to low after ce 1 is brought to low. ? t vpl is specified from the falling edge of either ce 1 or adv whichever comes late. at least one valid clock edge must be input during adv = l. ? t vsck and t clck are applied to the 1st valid clock edge during adv =l. case #1 case #2 address valid valid
mb82dbr08163a- 70l 45 (20) synchronous read timing 1 (oe control) clk adv ce1 oe we lb, ub wait dq rl = 5 t asvl t ahv t ckvh t vpl t ascl t clck t vsck t rcb high t olq t blq t oltl t olz t cktv t cktx t ac t ac t ac t ckqx t ckqx t ohz t ohtz t ckbh t ckoh t cp t clck t ascl t vpl t vhvl t ckvh t vsck t asvl q bl q 1 high-z high-z note : this timing diagram assumes ce2 = h, the valid clock edge on rising edge and bl = 8 or 16. address address valid address valid
mb82dbr08163a- 70l 46 (21) synchronous read timing 2 (ce 1 control) clk adv ce1 oe we wait dq rl = 5 t asvl t ahv t ckvh t vpl t ascl t clck t vsck t rcb high t cltl t clz t cktv t cktx t ac t ac t ac t ckqx t ckqx t chz t cltl t ckbh t cp t clck t vpl q bl t clz t chtz t ckclh t vhvl t ckvh t asvl t vsck t ahv t ascl q 1 l b, ub note : this timing diagram assumes ce2 = h, the valid clock edge on rising edge and bl = 8 or 16. address address valid address valid
mb82dbr08163a- 70l 47 (22) synchronous read timing 3 (adv control) clk adv dq rl = 5 t asvl t ahv t ckvh t vpl t vsck t rcb high t cktv t cktx t ac t ac t ac t ckqx t ckqx t vpl ce1 oe we wait t vhvl t ckvh t asvl t vsck t ahv q bl q 1 low low l b, ub t vltl t vltl note : this timing diagram assumes ce2 = h, the valid clock edge on rising edge and bl = 8 or 16. address address valid address valid
mb82dbr08163a- 70l 48 (23) synchronous write timing 1 (we level control) clk adv ce1 oe we wait dq rl = 5 t asvl t ahv t ckvh t vpl t ascl t clck t vsck t wcb t wlth t dsck t dhck t cp t vpl t wrb t ckvh t asvl t ahv t ascl high t clck t ckwh t ckbh t dsck t dsck t dhck t whtz t bs t bs t wld t vsck d 1 d 2 d bl high-z l b, ub note : this timing diagram assumes ce2 = h, th e valid clock edge on rising edge and bl = 8 or 16. address address valid address valid
mb82dbr08163a- 70l 49 (24) synchronous write timing 2 (we single clock pulse timing) clk adv ce1 oe we wait dq rl = 5 t asvl t ahv t ckvh t vpl t ascl t clck t vsck t wcb t wlth t dsck t dhck t cp t vpl t wrb t ckvh t asvl t ahv t ascl high t clck t ckclh t ckbh t dsck t dsck t dhck t chtz t bs t vsck t ckwh t wsck t wlth t ckwh t wsck t bs d 1 d 2 d bl high-z l b, ub note : this timing diagram assumes ce2 = h, th e valid clock edge on rising edge and bl = 8 or 16. address address valid address valid
mb82dbr08163a- 70l 50 (25) synchronous write timing 3 (adv control) clk adv ce1 oe we wait dq rl = 5 t asvl t ahv t ckvh t vpl t vsck t wcb t dsck t dhck t wrb t vpl t ckvh t asvl t ahv high t ckbh t dsck t dsck t dhck t bs t vsck t bs d 1 d 2 d bl l b, ub high note : this timing diagram assumes ce2 = h, the va lid clock edge on rising edge and bl = 8 or 16. address address valid address valid
mb82dbr08163a- 70l 51 (26) synchronous write timing 4 (we level control, single write) rl = 5 t ahv t ckvh t vpl tvsck t vpl t ckvh tahv clk adv ce1 oe we wait dq t ascl t clck t wrb t cp t clck high t wld t ckwh t bs t ckbh t bs t wlth t whtz t wlth t dsck t dhck t wcb d 1 t vsck t vsck t asvl t asvl t ahv t ascl high-z l b, ub notes : ? this timing diagram assumes ce2 = h, the valid clock edge on rising edge and single write operation. ? write data is latched on the valid clock edge. address address valid address valid
mb82dbr08163a- 70l 52 (27) synchronous read to write timing 1 (ce 1 control) rl = 5 t ahv t ckvh t vsck t asvl t vpl t vhvl t clck t ascl t cp t dsck t dhck t dsck t dhck t dsck t dhck t dsck t dhck t bs t chtz t clth t chz t ac t ckqx t ckqx t ckbh t ckclh t ckclh t ckbh d 1 d 2 d 3 d bl q bl-1 q bl clk adv ce1 oe we w ait dq l b,ub t wcb note : this timing diagram assumes ce2 = h, the valid clock edge on rising edge and bl = 8 or 16. address address valid
mb82dbr08163a- 70l 53 (28) synchronous read to write timing 2 (adv control) rl = 5 t ahv t ckvh t vsck t asvl t vpl t vhvl t dsck t dhck t dsck t dhck t dsck t dhck t dsck t dhck t bs t ohtz t wlth t ohz t ac t ckqx t ckqx t ckbh t ckwh t ckbh d 1 d 2 d 3 d bl q bl-1 q bl clk adv ce1 oe we w ait dq l b,ub t wld t ckoh note : this timing diagram assumes ce2 = h, the va lid clock edge on rising edge and bl = 8 or 16. address address valid
mb82dbr08163a- 70l 54 (29) synchronous write to read timing 1 (ce 1 control) t ahv t ckvh t asvl t vpl t dsck t dhck t dsck t dhck clk adv ce1 oe we w ait dq l b,ub rl = 5 t ckclh t cp t wrb t chtz t cltl t ac t ac t cktx t cktv t ckqx t ckqx t clz t clck high-z d bl-1 d bl q 1 q 2 t ckbh t vsck t ascl note : this timing diagram assumes ce2 = h, the va lid clock edge on rising edge and bl = 8 or 16. address address valid
mb82dbr08163a- 70l 55 (30) synchronous write to read timing 2 (adv control) t ahv t ckvh t asvl t vpl t dsck t dhck t dsck t dhck clk adv ce1 oe we w ait dq l b,ub rl = 5 t ckwh t wrb t blq t whtz t oltl t ac t ac t cktx t cktv t ckqx t ckqx t olz d bl-1 d bl q 1 q 2 t olq high-z t ckbh t vsck low note : this timing diagram assumes ce2 = h, the valid clock edge on rising edge and bl = 8 or 16. address address valid
mb82dbr08163a- 70l 56 (31) power-up timing 1 (32) power-up timing 2 *1 : v ddq shall be applied and reached the specified minimum level prior to v dd applied. *2 : the both of ce 1 and ce2 shall be brought to high together with v ddq prior to v dd applied. otherwise ?(32) power-up timing 2? must be applied for proper operation. *3 : the t chh specifies after v dd reaches specified minimum level and applicable to both ce 1 and ce2. ce1 ce2 * 2 * 2 v ddq 0 v v dd 0 v t chh * 3 v ddq (min) * 1 v dd (min) * 1, * 2 *1 : v ddq shall be applied and reached the specified minimum level prior to v dd applied. *2 : the t c2hl specifies from ce2 low to high transition after v dd reaches specified minimum level. if ce2 became high prior to v dd reached specified minimum level, t c2hl is defined from v dd minimum. *3 : ce 1 shall be brought to high prior to or to gether with ce2 low to high transition. *4 : if transition time of v dd (from 0 v to v dd (min) ) is longer than 10 ms, ?(31) power-up timing 1? must be applied. ce1 ce2 * 3 v ddq 0 v v dd * 4 0 v t c2hl * 2 t csp t c2lp t chh t chs t c2hl * 2 v ddq (min) * 1 v dd (min) * 1
mb82dbr08163a- 70l 57 (33) power down entry and exit timing (34) standby entry timing after read or write t chs t chh (t chhp ) t c2lp t csp high-z c e1 c e2 dq note : this power down mode can be also used as a reset timing if ?power-up timing? above could not be satisfied and power down program wa s not performed prior to this reset. power down entry power down mode power down exit t chox t chwx c e1 oe we note : both t chox and t chwx define the earliest entry timing for standby mode. active (read) standby active (write) standby
mb82dbr08163a- 70l 58 (35) configuration register set timing 1 (asynchronous operation) ce1 we l b, ub* 4 oe dq* 3 t rc t rc t wc t wc t wc t wc t cp t cp t cp t cp t cp t cp * 3 (t rc) rda rda rda x x rdb msb* 1 msb* 1 msb* 1 msb* 1 msb* 1 address cycle #1 cycle #2 cycle #3 cycle #4 cycle #5 cycle #6 *1 : the all address inputs must be high from cycle #1 to #5. *2 : the address key must confirm the format specified in ? functional description?. if not, the operation and data are not guaranteed. *3 : after t cp or t rc following cycle #6, the configuration register set is completed and returned to the normal operation. t cp and t rc are applicable to return ing to asynchronous mode and to synchronous mode respectively. *4 : byte read or write is available in addition to word read or write. at least one byte control signal (lb or ub ) need to be low. key * 2
mb82dbr08163a- 70l 59 (36) configuration register set timing 2 (synchronous operation) msb* 1 msb* 1 msb* 1 msb* 1 msb* 1 rl rl-1 t trb t trb t trb t trb t trb t trb t rcb t wcb t wcb t wcb t wcb t rcb rda rda rda x x rdb clk adv ce1 oe we dq l b,ub* rl-1 rl-1 rl-1 rl 4 * 3 *1 : the all address inputs must be high from cycle #1 to #5. *2 : the address key must confirm the format specified in ? functional description?. if not, the operation and data are not guaranteed. *3 : after t trb following cycle #6, the configuration register set is completed and returned to the normal operation. *4 : byte read or write is available in addition to word read or write. at least one byte control signal (lb or ub ) need to be low. address key* 2 cycle #1 cycle #2 cycle #3 cycle #4 cycle #5 cycle #6
mb82dbr08163a- 70l 60 package for engineering samples pin assignment dj h g f e 2 1 a m l k c b 8 3 4 5 6 7 n.c. a 11 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. a 8 a 15 a 12 a 21 a 13 a 22 a 14 a 16 n.c. n.c. dq 16 v ss dq 8 a 19 ce2 a 9 a 20 adv ub wait a 18 a 6 a 3 a 5 a 2 a 4 a 1 v ss a 0 a 10 a 17 dq 7 dq 2 dq 14 dq 5 dq 13 v dd dq 4 dq 10 v ddq dq 11 n.c. dq 1 dq 15 dq 6 n.c. dq 12 dq 3 dq 9 we clk lb a 7 oe ce1 (top view) (bga-71p-m03)
mb82dbr08163a- 70l 61 pin description pin name description a 22 to a 0 address input ce 1 chip enable 1 (low active) ce2 chip enable 2 (high active) we write enable (low active) oe output enable (low active) lb lower byte control (low active) ub upper byte control (low active) clk clock input adv address valid input (low active) wait wait output dq 8 to dq 1 lower byte data input/output dq 16 to dq 9 upper byte data input/output v dd power supply voltage v ddq i/o power supply voltage v ss ground n.c. no connection
mb82dbr08163a- 70l 62 package capacitance (f = 1 mhz, t a = + 25 c) package view parameter symbol test conditions value unit min typ max address input capacitance c in1 v in = 0 v ?? 5pf control input capacitance c in2 v in = 0 v ?? 5pf data input/output capacitance c i / o v io = 0 v ?? 8pf 71-pin plastic fbga ( bga - 71p - m03 )
mb82dbr08163a- 70l 63 package dimension ordering information 71-pin plastic fbga (bga-71p-m03) dimensions in mm (inches) note : the values in parentheses are reference values. part number shipping form remarks MB82DBR08163A-70LWT wafer c 2003 fujitsu limited b71003s-c-1-1 11.000.10(.433.004) 7.00 0.10 (.276 .004) index-mark area a b c d e f g h j k l m 1 2 3 4 5 6 7 8 s 1.09 +0.11 ?0.10 +.004 ? .004 .043 (.015 .004) 0.39 0.10 (stand off) (seated height) 0.20(.008) s b 0.10(.004) s 0.10(.004) s a s 0.20(.008) ref 0.80(.031) b ref 0.40(.016) ref 0.80(.031) a ref 0.40(.016) ab s m ? 0.08(.003) 71-?0.45 +0.10 ? 0.05 +.004 ? .002 71- ? .018
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